(a) Fields of the Invention
The present invention relates to field effect transistors capable of effectively supplying hydrogen to a gate insulating film during hydrogen sintering, and to fabrication methods thereof.
(b) Description of Related Art
With shrinking of design rules of semiconductor devices, circuit integration thereof dramatically increases, which in turn enables incorporation of more than one hundred million field effect (Metal Insulator Semiconductor) transistors on one chip. In order to fabricate such a chip, strong demand is made of not only advancement of ultrafine processing technologies, such as lithography and etching, which require processing accuracy on the order of several tens of nanometers, but also technological development for improving a margin of processing size or alignment deviation.
As one of the techniques for improving the margin of processing size or alignment deviation, a SAC (Self Aligned Contact hole) method in a contact plug formation process is often employed as an effective method. This is the method for improving the margin in the manner in which a gate electrode is fully covered with a silicon nitride film to provide a high etching selectivity with respect to a silicon oxide film constituting an interlayer film for the contact plug.
FIG. 10 shows a cross-sectional structure of a conventional semiconductor device including a transistor formed by a SAC method.
Referring to FIG. 10, above a semiconductor substrate 501, a gate electrode 503 having a silicide layer 507 in its upper portion is formed with a gate insulating film 502 interposed therebetween. A p-type source/drain region 504 with a shallow junction depth is formed in a region of the semiconductor substrate 501 located below each side of the gate electrode 503. A sidewall 505 is formed on side surfaces of the silicide layer 507, the gate electrode 503, and the gate insulating film 502. In a region of the semiconductor substrate 501 located below an outer side of the sidewall 505, a p-type source/drain region 506 with a great junction depth is formed which has a silicide layer 507 in its upper portion. Over the entire surface of the semiconductor substrate 501, a contact liner film 508 of a silicon nitride film is formed to cover the gate electrode 503 and the sidewall 505. An interlayer insulating film 509 of a silicon oxide film is formed on the contact liner film 508. In the interlayer insulating film 509 and the contact liner film 508, a contact plug 510 is formed which penetrates the interlayer insulating film 509 and the contact liner film 508 and of which the bottom end reaches the silicide layer 507.
The structure described above can be employed to improve an etching margin in forming the contact plug 510. To be more specific, in forming a contact hole for formation of the contact plug 510, the contact hole formation process is divided into two steps composed of: the step of etching, using the contact liner film 508 as an etch stop film, the silicon oxide film constituting the interlayer insulating film 509; and the subsequent step of etching the contact liner film 508. Thereby, even though an excessive amount of etching is performed on the silicon oxide film, additional etching performed on the sidewall 505 or the semiconductor substrate 501 can be blocked.
However, when the SAC structure is employed in which the contact liner film 508 of a silicon nitride film is formed to fully cover the gate electrode 503, hydrogen supply to the gate insulating film becomes difficult in a hydrogen sintering process for recovering damages in the gate insulating film 502. This causes a trouble that the reliability of the transistor, in particular NBTI (Negative Bias Temperature Instability) of the p-channel MIS transistor deteriorates. Specifically, since the silicon nitride film constituting the contact liner film 508 has a very strong effect of blocking hydrogen, only hydrogen passing through the contact plug 510 is supplied to the gate insulating film 502 in the hydrogen sintering. Thus, the absolute amount of hydrogen supplied to the gate insulating film 502 becomes very small, which makes it difficult to recover damages in the gate insulating film 502. Therefore, the threshold voltage of the PMIS transistor fluctuates with time.
To deal with this trouble, another approach to effectively recovering damages in the gate insulating film 502 even in the case of using a silicon nitride film as the contact liner film 508 is proposed (see, for example, Japanese Unexamined Patent Publication No. 2005-79255). In this approach, a contact liner film is formed of a silicon nitride film containing a great amount of hydrogen, and then the film is subjected to thermal annealing to supply hydrogen from the silicon nitride film to the gate insulating film 502, thereby recovering damages in the gate insulating film 502.
For the approach described in the aforementioned Japanese Unexamined Patent Publication No. 2005-79255, however, the amount of hydrogen supplied to the gate insulating film is limited to the amount of hydrogen contained in the contact liner film. In order to advance transistor miniaturization, it is also necessary to reduce the thickness of the contact liner film. Thus, for a fine transistor, the amount of hydrogen supplied to a gate insulating film decreases, which disadvantageously makes it difficult to recover damages in the gate insulating film.